# Lecture24 - University of Washington

Lecture 25 Logistics HW8 posted today, due 12/5 Lab9 this week No Class for the rest of the week! Last lecture Robot ant in maze Started on FSM simplification a little bit Today More on FSM simplification CSE370, Lecture 2522 1 The WHY slide FSM minimization It is best to minimize FSM before expressing it as a logic circuit. As you saw in the ant robot example, minimization step is about looking for some patterns and merging states. There are systematic ways to do this (rather than the way wed done it for the ant example) and we will learn them here. CSE370, Lecture 2522 2 Two Methods for FSM Minimization Row matching Easier to do by hand

Misses minimization opportunities Implication table Guaranteed to find the most reduced FSM More complicated algorithm (but still relatively easy to write a program to do it) CSE370, Lecture 2522 3 Simple row matching does not guarantee most reduced state machine Present State S0 CSE370, Lecture 2522 Next State X=0 X=1 S0 S1 Output 0 S1 S1

S2 1 S2 S2 S1 0 4 The Implication chart method Heres a slightly funkier FSM as an example CSE370, Lecture 2522 5 Step 1: Draw the table CSE370, Lecture 2522 6 Step 2: Consider the outputs CSE370, Lecture 2522

7 Step 3: Add transition pairs C-R 0 1 CSE370, Lecture 2522 8 Step 3: Add transition pairs C-R 0 1 Implied State Pairs CSE370, Lecture 2522 9 Step 4 (repeated): Consider transitions CSE370, Lecture 2522 10 Final reduced FSM

CSE370, Lecture 2522 11 Odd parity checker revisited Present State S0 Next State X=0 X=1 S0 S1 Output 0 S1 S1 S2 1 S2 S2 S1

0 CSE370, Lecture 2522 S1 S2 S0-S2 S1S1 S0 S1 12 More complex state minimization Multiple input example inputs here 00 00 S0 [1] 10 10 01 11

00 01 01 11 00 S2 [1] 10 01 11 10 01 S4 [1] S3 [0] 11 10 10 00 S1 [0] 11

S5 [0] 01 00 11 CSE370, Lecture 2522 present state S0 S1 S2 S3 S4 S5 00 S0 S0 S1 S1 S0 S1 next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4

S0 S4 S5 S1 S2 S5 S4 S0 S5 output 1 0 1 0 1 0 symbolic state transition table 13 Minimized FSM Implication chart method cross out incompatible states based on outputs then cross out more cells if indexed chart entries are already crossed out S1 present state S0 S1 S2 S3 S4 S5

00 S0 S0 S1 S1 S0 S1 next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4 S0 S4 S5 S1 S2 S5 S4 S0 S5 output 1 0 1 0 1 0 S0-S1 S2 S1-S3 S2-S2 S3-S4 S3 S0-S0 S4 S1-S1 S2-S2

S3-S5 S5 CSE370, Lecture 2522 S0 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S1 S1-S0 S3-S1 S2-S2 S4-S5 S2 S1-S1 S0-S4 S4-S0 S5-S5 S3 S4

14 Minimized FSM present state S0 S1 S2 S3 S4 S5 S1 S0-S1 S2 S1-S3 S2-S2 S3-S4 S3 S0-S0 S4 S1-S1 S2-S2 S3-S5 S5 S0 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0

S4-S5 S1 S1-S0 S3-S1 S2-S2 S4-S5 S2 CSE370, Lecture 2522 S1-S1 S0-S4 S4-S0 S5-S5 S3 present state S0' S1 S2 S3' S4 00 S0 S0 S1 S1 S0

S1 next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4 S0 S4 S5 S1 S2 S5 S4 S0 S5 00 S0' S0' S1 S1 next state 01 10 11 S1 S2 S3' S3' S1 S3' S3' S2 S0' S0' S0' S3' output 1 0 1 0 1 0 output 1

0 1 0 minimized state table (S0==S4) (S3==S5) 15 Minimizing incompletely specified FSMs Equivalence of states is transitive when machine is fully specified But its not transitive when don't cares are present e.g., state S0 X 0 S1 1 X S2 X 1 output S1 is compatible with both S0 and S2 but S0 and S2 are incompatible Hard to determining best grouping of states to yield the smallest number of final states CSE370, Lecture 2522 16 Minimizing FSMs isnt always good Two FSMs for 0->1 edge detection

CSE370, Lecture 2522 17 Minimal state diagram -> not necessarily best circuit In 0 0 0 1 1 1 Q1 0 0 1 0 0 1 1 Q0 0 1 1 0 1

1 0 Q1+ 0 0 0 0 1 1 0 Q0+ 0 0 0 1 1 1 0 Q1+ = In (Q1 xor Q0) Q0+ = In Q1 Q0 Out = Q1 Q0 CSE370, Lecture 2522 18 Minimal state diagram -> not necessarily best circuit

In Q Q Q Q 1 CSE370, Lecture 2522 + 1 0 + 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0

0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1

1 1 Q1+ = Q0 Q0+ = In Out = Q1 Q0 19 A little perspective These kinds of optimizations are what CAD(Computer Aided Design)/EDA(Electronic Design Automation) is all about The interesting problems are almost always computationally intractable to solve optimally People really care about the automation of the design of billion-transistor chips CSE370, Lecture 2522 20

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