CECS470 - Rochester Institute of Technology

CECS470 - Rochester Institute of Technology

Mainstream Computer System Components Double Date Rate (DDR) SDRAM One channel = 8 bytes = 64 bits wide Current DDR3 SDRAM Example: PC3-12800 (DDR3-1600) 200 MHz (internal base chip clock) 8-way interleaved (8-banks) ~12.8 GBYTES/SEC (peak) (one 64bit channel) ~25.6 GBYTES/SEC (peak) (two 64bit channels e,g AMD x4, x6) ~38.4 GBYTES/SEC (peak) (three 64bit channels e.g Intel Core i7) PC2-6400 (DDR2-800) 200 MHz (internal base chip clock) 64-128 bits wide 4-way interleaved (4-banks) ~6.4 GBYTES/SEC (peak) (one 64bit channel) ~12.8 GBYTES/SEC (peak) (two 64bit channels) CPU Core 2 GHz - 3.5 GHz 4-way Superscaler (RISC or RISC-core (x86): Dynamic scheduling, Hardware speculation Multiple FP, integer FUs, Dynamic branch prediction L1 CPU L2 L3 Caches SRAM All Non-blocking caches L1 16-128K 2-8 way set associative (usually separate/split) L2 256K- 4M 8-16 way set associative (unified) L3 4-24M 16-64 way set associative (unified) (FSB) System Bus SRAM Off or On-chip Single Date Rate SDRAM PC100/PC133 100-133MHz (base chip clock)

64-128 bits wide 2-way inteleaved (2-banks) ~ 900 MBYTES/SEC peak (64bit) Memory Bus I/O Buses NICs Controllers Memory Disks Displays Keyboards System Memory (DRAM) North Bridge Examples: AMD K8: HyperTransport Alpha, AMD K7: EV6, 200-400 MHz Intel PII, PIII: GTL+ 133 MHz Intel P4 800 MHz adapters Memory Controller DDR SDRAM Example: PC3200 (DDR-400) 200 MHz (base chip clock) 4-way interleaved (4-banks) ~3.2 GBYTES/SEC (peak) (one 64bit channel) ~6.4 GBYTES/SEC (two 64bit channels) One core or multi-core (2-8) per chip South Bridge Chipset Example: PCI, 33-66MHz 32-64 bits wide 133-528 MBYTES/SEC PCI-X 133MHz 64 bit 1024 MBYTES/SEC

Networks I/O Devices: AKA System Core Logic System Bus = CPU-Memory Bus = Front Side Bus (FSB) I/O Subsystem: 4th Edition in Chapter 6 (3rd Edition in Chapter 7) CMPE550 - Shaaban #1 lec # 10 Spring 2017 4-24-2017 The Memory Hierarchy Review of Memory Hierarchy & Cache Basics (from 350) Cache Basics: CPU Performance Evaluation with Cache Classification of Steady-State Cache Misses: The Three Cs of cache Misses Cache Write Policies/Performance Evaluation Cache Write Miss Policies Multi-Level Caches & Performance Main Memory: Performance Metrics: Latency & Bandwidth Key DRAM Timing Parameters Cache exploits access locality to: 1 Lower AMAT by hiding long main memory access latency.

2 Lower demands on main memory bandwidth. 4th Edition: Chapter 5.3 3rd Edition: Chapter 5.8, 5.9 DRAM System Memory Generations Basic Memory Bandwidth Improvement/Miss Penalty Reduction Techniques Techniques To Improve Cache Performance: Reduce Miss Rate Reduce Cache Miss Penalty Reduce Cache Hit Time i.e Memory latency reduction Virtual Memory Benefits, Issues/Strategies Basic Virtual Physical Address Translation: Page Tables Speeding Up Address Translation: Translation Lookaside Buffer (TLB) CMPE550 - Shaaban #2 lec # 10 Spring 2017 4-24-2017 Addressing The CPU/Memory Performance Gap: Memory Access Latency Reduction & Hiding Techniques Memory Latency Reduction Techniques: Reduce it! Faster Dynamic RAM (DRAM) Cells: Depends on VLSI processing technology. Wider Memory Bus Width/Interface: Fewer memory bus accesses needed Burst Mode Memory Access e.g 128 vs. 64 bits Multiple Memory Banks:

At DRAM chip level (SDR, DDR, DDR2, DDR3 SDRAM), module or channel levels. Basic Memory Bandwidth Improvement/Miss Penalty Reduction Techniques Integration of Memory Controller with Processor: e.g AMD and Intels current processor architecture New Emerging Faster RAM Technologies: New Types of RAM Cells: e.g. Magnetoresistive RAM (MRAM), Zero-capacitor RAM (Z-RAM), Thyristor RAM (T-RAM) ... 3D-Stacked Memory: e.g Micron's Hybrid Memory Cube (HMC), AMD's High Bandwidth Memory (HBM). Memory Latency Hiding Techniques: Memory Hierarchy: Hierarchy One or more levels of smaller and faster memory (SRAM-based cache) onor off-chip that exploit program access locality to hideHide long it! main memory latency. Lecture 8 Pre-Fetching: Request instructions and/or data from memory before actually needed to hide long memory access latency. CMPE550 - Shaaban #3 lec # 10 Spring 2017 4-24-2017 Main Memory Main (or system) memory generally utilizes Dynamic RAM (DRAM), which use a single transistor to store a bit, but require a periodic data refresh by reading every row increasing cycle time. DRAM: Slow but high density Static RAM may be used for main memory if the added expense, low density, high power consumption, and complexity is feasible (e.g. Cray Vector Supercomputers). Main memory performance is affected by: SRAM: Fast but low density Memory latency: Affects cache miss penalty, M. Measured by: Memory Access time: The time it takes between a memory access request is issued to main memory and the time the requested information is available to cache/CPU. Memory Cycle time: The minimum time between requests to memory (greater than access time in DRAM to allow address lines to be stable) Peak or Nominal Memory bandwidth: The maximum sustained data transfer rate between main memory and cache/CPU. In current memory technologies (e.g Double Data Rate SDRAM) published peak memory

bandwidth does not take account most of the memory access latency. This leads to achievable realistic memory bandwidth < peak memory bandwidth 4th Edition: Chapter 5.3 3rd Edition: Chapter 5.8, 5.9 Or maximum effective memory bandwidth CMPE550 - Shaaban #4 lec # 10 Spring 2017 4-24-2017 Logical Dynamic RAM (DRAM) Chip Organization Now: 16 Gbit/chip (16 Mbit) 1 - Supply Row Address 2- Supply Column Address 3- Read/Write Data Column Decoder Sense Amps & I/O 14 2 A0A13 0 MemoryArray Shared Pins Q (16,384 x 16,384) Data Out D, Q share the same pins Word Line Basic Steps: Control Signals: 1 - Row Access Strobe (RAS): Low to latch row address 2- Column Address Strobe (CAS): Low to latch column address 3- Write Enable (WE) or Output Enable (OE) 4- Wait for data to be ready 1 - Supply Row Address D Data In

Row/Column Address Row Decoder 1 2- Supply Column Address 3- Get Data Storage Cell (Single transistor per bit) A periodic data refresh is required by reading every bit CMPE550 - Shaaban #5 lec # 10 Spring 2017 4-24-2017 3 Four Key DRAM Timing Parameters 1 tRAC: Minimum time from RAS (Row Access Strobe) line falling (activated) to the valid data output. Used to be quoted as the nominal speed of a DRAM chip For a typical 64Mb DRAM tRAC = 60 ns 2 tRC: Minimum time from the start of one row access to the start of the next (memory cycle time). tRC = tRAC + RAS Precharge Time tRC = 110 ns for a 64Mbit DRAM with a tRAC of 60 ns 3 tCAC: Minimum time from CAS (Column Access Strobe) line falling to valid data output. 12 ns for a 64Mbit DRAM with a tRAC of 60 ns 4 tPC: Minimum time from the start of one column access to the start of the next. tPC = tCAC + CAS Precharge Time About 25 ns for a 64Mbit DRAM with a tRAC of 60 ns 1 - Supply Row Address 2- Supply Column Address 3- Get Data CMPE550 - Shaaban #6 lec # 10 Spring 2017 4-24-2017

Simplified Asynchronous DRAM Read Timing Memory Cycle Time = tRC = tRAC + RAS Precharge Time 2 tRC Non-burst Mode Memory Access Example (late 1970s) (memory cycle time) Recovery Time tPC 1 4 (memory access time) 3 1 2 3 4 tRAC: Minimum time from RAS (Row Access Strobe) line falling to the valid data output. tRC: Minimum time from the start of one row access to the start of the next (memory cycle time). tCAC: minimum time from CAS (Column Access Strobe) line falling to valid data output. tPC: minimum time from the start of one column access to the start of the next. Peak Memory Bandwidth = Memory bus width / Memory cycle time Example: Memory Bus Width = 8 Bytes Memory Cycle time = 200 ns Peak Memory Bandwidth = 8 / 200 x 10-9 = 40 x 106 Bytes/sec Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html CMPE550 - Shaaban #7 lec # 10 Spring 2017 4-24-2017 Simplified DRAM Speed Parameters Row Access Strobe (RAS)Time: (similar to tRAC): Effective Minimum time from RAS (Row Access Strobe) line falling (activated) to the first valid data output. A major component of memory latency. And cache miss penalty M Only improves ~ 5% every year. Column Access Strobe (CAS) Time/data transfer time:

(similar to tCAC) The minimum time required to read additional data by changing column address while keeping the same row address. Burst-Mode Access Along with memory bus width, determines peak memory bandwidth. e.g For SDRAM Peak Memory Bandwidth = Bus Width /(0.5 x tCAC) Example For PC100 SDRAM Memory bus width = 8 bytes tCAC = 20ns Peak Bandwidth = 8 x 100x106 = 800 x 106 bytes/sec Simplified SDRAM Burst-Mode Access Timing 40 ns RAS Memory Latency Burst length shown = 4 50 ns 1/2CAS 1/2CAS 60 ns For PC100 SDRAM: Clock = 100 MHz 70 ns 1/2CAS 80 ns 1/2CAS 1st 2nd 4th 3rd 8 bytes 8 bytes 8 bytes 8 bytes CMPE550 - Shaaban #8 lec # 10 Spring 2017 4-24-2017 DRAM Generations Chip Density (bits/chip) Size 1980 1983 1986 1989 1992 1996

1998 2000 2002 64 Kb 256 Kb 1 Mb 4 Mb 16 Mb 64 Mb 128 Mb 256 Mb 512 Mb RAS (ns) CAS (ns) Cycle Time Memory Type 150-180 120-150 100-120 80-100 60-80 50-70 50-70 45-65 40-60 75 50 25 20 15 12 10 7 5 250 ns 220 ns 190 ns 165 ns 120 ns 110 ns 100 ns 90 ns 80 ns Page Mode Page Mode

8000:1 (Capacity) 2013 2016 8 Gb 16 Gb ~ RAS+ 15:1 (~bandwidth) Fast Page Mode EDO PC66 SDRAM PC100 SDRAM PC133 SDRAM PC2700 DDR SDRAM 3:1 (Latency) Peak PC3200 DDR (2003) DDR2 SDRAM (2004) DDR3 SDRAM (2007) A major factor in cache miss penalty M DDR4 SDRAM (2014) CMPE550 - Shaaban #9 lec # 10 Spring 2017 4-24-2017 Asynchronous DRAM Synchronous DRAM Year Effective Asynchronous DRAM: Page Mode DRAM (Early 1980s) Last system memory type to use non-burst access mode 1 - Supply Row Address 2- Supply Column Address 3- Read/Write Data

Non-burst Mode Memory Access Memory Cycle Time 1 - Supply Row Address 2- Supply Column Address 3- Get Data CMPE550 - Shaaban #10 lec # 10 Spring 2017 4-24-2017 Fast Page Mode (FPM) DRAM (late 1980s) (Change) (constant for entire burst access) The first burst mode DRAM (memory access time) 1 2 A read burst of length 4 shown Constant 1 2 3 4 Burst Mode Memory Access 3 4 Change CMPE550 - Shaaban #11 lec # 10 Spring 2017 4-24-2017 Simplified Asynchronous Fast Page Mode (FPM) DRAM Read Timing (late 80s) FPM DRAM speed rated using tRAC ~ 50-70ns tPC

(memory access time) First 8 bytes Second 8 bytes etc. A read burst of length 4 shown Typical timing at 66 MHz : 5-3-3-3 (burst of length 4) For bus width = 64 bits = 8 bytes cache block size = 32 bytes It takes = 5+3+3+3 = 14 memory cycles or 15 ns x 14 = 210 ns to read 32 byte block Miss penalty for CPU running at 1 GHz = M = 15 x 14 = 210 CPU cycles One memory cycle at 66 MHz = 1000/66 = 15 CPU cycles at 1 GHz 1 2 3 4 5 cycles 3 cycles 3 cycles 3 cycles CMPE550 - Shaaban #12 lec # 10 Spring 2017 4-24-2017 Simplified Asynchronous Extended Data Out (EDO) (early 90s) DRAM Read Timing Extended Data Out DRAM operates in a similar fashion to Fast Page Mode DRAM except putting data from one read on the output pins at the same time the column address for the next read is being latched in. EDO DRAM speed rated using tRAC ~ 40-60ns (memory access time) Typical timing at 66 MHz : 5-2-2-2 (burst of length 4) For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 2 = 264 Mbytes/sec It takes = 5+2+2+2 = 11 memory cycles or 15 ns x 11 = 165 ns to read 32 byte cache block Minimum Read Miss penalty for CPU running at 1 GHz = M = 11 x 15 = 165 CPU cycles One memory cycle at 66 MHz = 1000/66 = 15 CPU cycles at 1 GHz Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html

CMPE550 - Shaaban #13 lec # 10 Spring 2017 4-24-2017 Basic Memory Bandwidth Improvement/Miss Penalty (M) Latency Improvement/ Reduction Techniques 1 Wider Main Memory (CPU-Memory Bus/Interface): wider FSB ? Memory bus width is increased to a number of words (usually up to the size of a cache block). Memory bandwidth is proportional to memory bus width. e.g Doubling the width of cache and memory doubles potential memory bandwidth available to the CPU. The miss penalty is reduced since fewer memory bus accesses are needed to fill a e.g 128 bit (16 bytes) memory bus instead of 64 bits (8 bytes) now 24 bytes (192 bits) cache block on a miss. Interleaved (Multi-Bank) Memory: 2 Memory is organized as a number of independent banks. Multiple interleaved memory reads or writes are accomplished by sending memory addresses to several memory banks at once or pipeline access to the banks. Interleaving factor: Refers to the mapping of memory addressees to memory banks. Goal reduce bank conflicts. e.g. using 4 banks (width one word), bank 0 has all words whose address is: (word address mod) 4 = 0 Burst Mode Memory Access 3 The above three techniques can also be applied to any cache level to reduce cache hit time and increase cache bandwidth. CMPE550 - Shaaban #14 lec # 10 Spring 2017 4-24-2017 i.e. Multiple Memory Banks Wider memory, bus and cache (highest performance) + (FSB) Narrow bus and cache

with interleaved memory + banks Burst (FSB) Mode Access Three examples of bus width, memory width, and memory interleaving to achieve higher memory bandwidth Simplest design: Everything is the width of one word for example (lowest performance) Front Side Bus (FSB) = System Bus = CPU-memory Bus CMPE550 - Shaaban #15 lec # 10 Spring 2017 4-24-2017 Four Way (Four Banks) Interleaved Memory Memory Bank Number Sequential Mapping of Memory Addresses To Memory Banks Example Address Within Bank Bank 0 Bank 1 Bank 2 Bank 3 0 4 8 12 16 20 .. 1 5 9 13 17 21

.. 2 6 10 14 18 22 .. 3 7 11 15 19 23 .. Bank Width = One Word Bank Number = (Word Address) Mod (4) Cache Block ? Next Cache Block ? CMPE550 - Shaaban #16 lec # 10 Spring 2017 4-24-2017 Memory Bank Interleaving (Multi-Banked Memory) Can be applied at: 1- DRAM chip level (e.g SDRAM, DDR) 2- DRAM module level 3- DRAM channel level (One Memory Bank) Memory Bank Cycle Time Very long memory bank recovery time shown here One Memory Bank (4 banks similar to the organization of DDR SDRAM memory chips) Also DDR2 (DDR3 increases the number to 8 banks, while DDR4 increases it to 16 banks) Pipeline access to different memory banks to increase effective bandwidth

Memory Bank Cycle Time Four Memory Banks Number of banks Number of cycles to access word in a bank Bank interleaving does not reduce latency of accesses to the same bank CMPE550 - Shaaban #17 lec # 10 Spring 2017 4-24-2017 Synchronous DRAM Generations Summary All Use: 1- Fixed Clock Rate 2- Burst-Mode Access 3- Multiple Banks per DRAM chip For Peak Bandwidth: Initial burst latency not taken into account SDR (Single Data Rate) SDRAM DDR2 DDR3 DDR4 2002 2004 2007 2014 2 4 4 8 16 PC100 DDR400 (PC-3200) DDR2-800 DDR3-1600 DDR4-3200 (PC2-6400) (PC3-12800) (PC4-25600)

Internal Base Frequency 100 MHz 200 MHz 200 MHz 200 MHz 200 MHz External Interface Frequency 100 MHz 200 MHz 400 MHz 800 MHz 1600 MHz 0.8 GB/s (8 x 0.1) 3.2 GB/s 6.4 GB/s 12.8 GB/s 25.6 GB/s (8 x 0.2 x 2) (8 x 0.2 x 4) (8 x 0.2 x 8) (8 x 0.2 x 16) Year of Introduction # of Banks Per DRAM Chip Example Peak Nominal Bandwidth (per 8 byte module) Latency Range SDR DDR (Double Data Rate) SDRAM Late 1990s 60-90 ns DDR 45-60 ns

35-50 ns 30-45 ns 25-40 ns ? The latencies given only account for memory module latency and do not include memory controller latency or other address/data line delays. Thus realistic access latency is longer All synchronous memory types above use burst-mode access with multiple memory banks per DRAM chip CMPE550 - Shaaban #18 lec # 10 Spring 2017 4-24-2017 SDR SDRAM Peak Memory Bandwidth = = Bus Width /(0.5 x tCAC) SDR = Single Data Rate = Bus Width x Clock rate (Data Lines) Synchronous Dynamic RAM, (SDR SDRAM) Organization (mid 90s) A SDRAM speed is rated at max. clock speed supported: 100MHZ = PC100 133MHZ = PC133 SDR = Single Data Rate DDR SDRAM DDR = Double Data Rate (late 90s - 2006) organization is similar but four banks are used in each DDR Also DDR2 SDRAM chip instead of two. Address Lines (DDR3 increases the number of banks to 8 banks) Data transfer on both rising and falling edges of the clock DDR SDRAM rated by maximum

or peak memory bandwidth PC3200 = 8 bytes x 200 MHz x 2 DDR SDRAM Peak Memory Bandwidth = = Bus Width /(0.25 x tCAC) DDR = Double Data Rate = Bus Width x Clock rate x 2 1 1 2 2 3 3 4 4 5 6 SDRAM 7 DDR SDRAM Timing Comparison = 3200 Mbytes/sec CMPE550 - Shaaban #19 lec # 10 Spring 2017 4-24-2017 Comparison of Synchronous Dynamic RAM SDRAM Generations: DDR2 Vs. DDR and SDR SDRAM For DDR3: The trend continues with another external frequency doubling Single Data Rate (SDR) SDRAM transfers data on every rising edge of the clock. 4258 MB/s = 8 x 133 x 4 Whereas both DDR and DDR2 are double pumped; they transfer data on the rising and falling edges of the clock. DDR2 vs. DDR: DDR2 doubles bus frequency for the same physical DRAM chip clock rate (as shown), thus doubling the effective data rate another time. Ability for much higher clock speeds than DDR, due to design improvements (still 4-banks per chip): DDR2's bus frequency is boosted

by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. Shown: DDR2-533 (PC2-4200) ~ 4.2 GB/s peak bandwidth 4 Banks DDR2 2128 MB/s = 8 x 133 x 2 Shown: DDR-266 (PC-2100) ~ 2.1 GB/s peak bandwidth 4 Banks DDR 1064 MB/s = 8 x 133 However, latency vs. DDR is greatly increased as a trade-off. Internal Base Frequency = 133 MHz Shown: PC133 ~ 1.05 GB/s peak bandwidth 2 Banks SDR Peak bandwidth given for a single 64bit memory channel (i.e 8-byte memory bus width) Figure Source: http://www.elpida.com/pdfs/E0678E10.pdf CMPE550 - Shaaban #20 lec # 10 Spring 2017 4-24-2017 Simplified SDR SDRAM/DDR SDRAM Read Timing SDRAM clock cycle time ~ tCAC Twice as fast as SDR SDRAM? DDR SDRAM: Possible timing at 133 MHz (DDR x2) (PC2100 DDR SDRAM) : 5 - .5- .5- .5 For bus width = 64 bits = 8 bytes

Max. Bandwidth = 133 x 2 x 8 = 2128 Mbytes/sec It takes = 5+ .5 +.5 +.5 = 6.5 memory cycles or 7.5 ns x 6.5 = 49 ns to read 32 byte cache block Minimum Read Miss penalty for CPU running at 1 GHz = M = 7.5 x 6.5 = 49 CPU cycles (DDR SDRAM Max. Burst Length = 16) Latency (memory access time) Data Data Data Data Data Data Data Data DDR SDRAM (Late 90s-2006) (SDRAM Max. Burst Length = 8) SDR SDRAM Typical timing at 133 MHz (PC133 SDRAM) SDR SDRAM (mid 90s) : 5-1-1-1 For bus width = 64 bits = 8 bytes Max. Bandwidth = 133 x 8 = 1064 Mbytes/sec It takes = 5+1+1+1 = 8 memory cycles or 7.5 ns x 8 = 60 ns to read 32 byte cache block Minimum Read Miss penalty for CPU running at 1 GHz = M = 7.5 x 8 = 60 CPU cycles In this example for SRD SDRAM: M = 60 cycles for DDR SDRAM: M = 49 cycles Thus accounting for access latency DDR is 60/49 = 1.22 times faster Not twice as fast (2128/1064 = 2) as indicated by peak bandwidth! CMPE550 - Shaaban #21 lec # 10 Spring 2017 4-24-2017 The Impact of Larger Cache Block Size on Miss Rate A larger cache block size improves cache performance by taking better advantage of spatial locality However, for a fixed cache size, larger block sizes mean fewer cache block frames Performance keeps improving to a limit when the fewer number of cache block frames increases conflicts and thus overall cache miss rate 25% 1K 20% Miss Rate 4K 15% 16K

10% 64K 5% 256K Block Size (bytes) X 256 128 64 32 For SPEC92 16 0% Larger cache block size improves spatial locality reducing compulsory misses 4th Edition: Appendix C.3 (3rd Edition: Chapter 5.5) CMPE550 - Shaaban #22 lec # 10 Spring 2017 4-24-2017 Memory Width, Interleaving: Performance Example (i.e Multiple Memory banks + Burst Mode Access) Given the following system parameters with single unified cache level L1 (ignoring write policy): Block size= 1 word Memory bus width= 1 word Miss rate =3% M = Miss penalty = 32 cycles (4 cycles to send address 24 cycles access time, 4 cycles to send a word to CPU) 4 cycles 24 cycles Memory access/instruction = 1.2 (Base system) Miss Penalty = M= 4 + 24 + 4 = 32 cycles 4 cycles

CPIexecution (ignoring cache misses) = 2 Miss rate (block size = 2 word = 8 bytes ) = 2% Miss rate (block size = 4 words = 16 bytes) = 1% The CPI of the base machine with 1-word blocks = 2 + (1.2 x 0.03 x 32) = 3.15 Increasing the block size to two words (64 bits) gives the following CPI: 32-bit bus and memory, no interleaving, M = 2 x 32 = 64 cycles 32-bit bus and memory, interleaved, M = 4 + 24 + 8 = 36 cycles 64-bit bus and memory, no interleaving, M = 32 cycles 32-bit bus and memory, no interleaving , M = 4 x 32 = 128 cycles 32-bit bus and memory, interleaved , M = 4 + 24 + 16 = 44 cycles 64-bit bus and memory, no interleaving, M = 2 x 32 = 64 cycles 64-bit bus and memory, interleaved, M = 4 + 24 + 8 = 36 cycles 128-bit bus and memory, no interleaving, M = 32 cycles 4 24 4 4 4 4 Miss Penalty = M = Number of CPU stall cycles for an access missed in cache and satisfied by main memory (miss rate = 2%) CPI = 2 + (1.2 x .02 x 64) = 3.54 CPI = 2 + (1.2 x .02 x 36) = 2.86 CPI = 2 + (1.2 x 0.02 x 32) = 2.77 Increasing the block size to four words (128 bits); resulting CPI: (For Base system) (miss rate = 1%) CPI = 2 + (1.2 x 0.01 x 128) = 3.54

CPI = 2 + (1.2 x 0.01 x 44) = 2.53 CPI = 2 + (1.2 x 0.01 x 64) = 2.77 CPI = 2 + (1.2 x 0.01 x 36) = 2.43 CPI = 2 + (1.2 x 0.01 x 32) = 2.38 CMPE550 - Shaaban #23 lec # 10 Spring 2017 4-24-2017 Three-Level Cache Example CPU with CPIexecution = 1.1 running at clock rate = 500 MHz 1.3 memory accesses per instruction. L1 cache operates at 500 MHz (no stalls on a hit in L1) with a miss rate of 5% L2 hit access time = 3 cycles (T2= 2 stall cycles per hit), local miss rate 40% L3 hit access time = 6 cycles (T3= 5 stall cycles per hit), local miss rate 50%, Memory access penalty, M= 100 cycles (stall cycles per access). Find CPI. With No Cache, With single L1, CPI = 1.1 + 1.3 x 100 = 131.1 CPI = 1.1 + 1.3 x .05 x 100 = 7.6 With L1, L2 CPI = 1.1 + 1.3 x (.05 x .6 x 2 + .05 x .4 x 100) = 3.778 All Unified Ignoring write policy CPI = CPIexecution + Mem Stall cycles per instruction Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per access Stall cycles per memory access = (1-H1) x H2 x T2 + (1-H1) x (1-H2) x H3 x T3 + (1-H1)(1-H2) (1-H3)x M = .05 x .6 x 2 + .05 x .4 x .5 x 5 + .05 x .4 x .5 x 100 = .06 + .05 + 1 = 1.11 AMAT = 1.11 + 1 = 2.11 cycles (vs. AMAT = 3.06 with L1, L2, vs. 5 with L1 only) CPI = 1.1 + 1.3 x 1.11 = 2.54 Speedup compared to L1 only = 7.6/2.54 = 3 Speedup compared to L1, L2 = 3.778/2.54 = 1.49 With L1, L2, L3 Repeated here from lecture 8 CMPE550 - Shaaban #24 lec # 10 Spring 2017 4-24-2017 Memory

Access Tree For Example 3-Level (All Unified) Cache Performance Memory Access Tree (Ignoring Write Policy) CPU Stall Cycles Per Memory Access CPI = CPI + (1 + fraction of loads and stores) x stalls per access CPU Memory Access (100%) execution CPI = H1 = .95 or 95% L1 Hit: L1 L2 Hit Access Time = 1 Stalls Per access = 0 Stalls= H1 x 0 = 0 ( No Stall) (1-H1) x H2 = .05 x .6 = .03 or 3% L1 Miss: % = (1-H1) = .05 or 5% L1 Miss, L2 Hit: Hit Access Time =T2 +1 = 3 Stalls per L2 Hit = T2 =2 Stalls =(1-H1) x H2 x T2 = .05 x .6 x 2 = .06 L3 1.1 + (1-H1) x (1-H2) x H3 = .05 x .4 x .5 = .01 or 1% L1 Miss, L2 Miss, L3 Hit: Hit Access Time =T3 +1 = 6 Stalls per L2 Hit = T3 = 5 T1 = 0 cycles T2 = 2 cycles T3 = 5 cycles

M = 100 cycles Stalls on a hit (1-H1)(1-H2)(1-H3) = .05 x .4 x .5 = .01 or 1% Full Miss L1 Miss, L2, Miss, L3 Miss: Miss Penalty = M = 100 Stalls = (1-H1)(1-H2)(1-H3) x M = .01 x 100 = 1 cycle = (1-H1) x H2 x T2 + (1-H1) x (1-H2) x H3 x T3 + (1-H1)(1-H2) (1-H3)x = .06 + .05 AMAT = 1 + Stall cycles per memory access T2 = 2 cycles ==Stalls hit access for Level 2 1 +per1.11 = 2.11 cycles Repeated here from lecture 8 T3 = 5 cycles = Stalls per hit access for Level 3 M= Memory Miss Penalty = M = 100 cycles H1 = 95% H2 = 60% H3 = 50% L1 Miss, L2 Miss: % = (1-H1)(1-H2) = .05 x .4 = .02 or 2% Stalls = (1-H1) x (1-H2) x H3 x T3 = .01 x 5 = .05 cycles Stall cycles per memory access M 1.3 x 1.11 = 2.54 +1 = 1.11 CMPE550 - Shaaban #25 lec # 10 Spring 2017 4-24-2017

Program Steady-State Bandwidth-Usage Example In the previous example with three levels of cache (all unified, ignore write policy) CPU with CPIexecution = 1.1 running at clock rate = 500 MHz 1.3 memory accesses per instruction. L1 cache operates at 500 MHz (no stalls on a hit in L1) with a miss rate of 5% L2 hit access time = 3 cycles (T2= 2 stall cycles per hit), local miss rate 40% L3 hit access time = 6 cycles (T3= 5 stall cycles per hit), local miss rate 50%, Memory access penalty, M= 100 cycles (stall cycles per access to deliver 32 bytes from main memory to CPU) We found the CPI: With No Cache, CPI = 1.1 + 1.3 x 100 = 131.1 With single L1, CPI = 1.1 + 1.3 x .05 x 100 = 7.6 With L1, L2 CPI = 1.1 + 1.3 x (.05 x .6 x 2 + .05 x .4 x 100) = 3.778 With L1, L2 , L3 CPI = 1.1 + 1.3 x 1.11 = 2.54 Assuming that all cache blocks are 32 bytes For each of the three cases with cache: A. What is the peak (or maximum) number of memory accesses and effective peak bandwidth for each cache level and main memory? B. What is the total number of memory accesses generated by the CPU per second? i.e. L1 only, L1 and L2, all three levels C. What percentage of these memory accesses reach each cache level/memory and what percentage of each cache level/memory bandwidth is used by the CPU? CMPE550 - Shaaban #26 lec # 10 Spring 2017 4-24-2017 Program Steady-State Bandwidth-Usage Example A. What is the peak (or maximum) number of memory accesses and effective peak bandwidth for each cache level and main memory? L1 cache requires 1 CPU cycle to deliver 32 bytes, thus: Maximum L1 accesses per second = 500x 106 accesses/second Maximum effective L1 bandwidth = 32 x 500x 106 = 16,000x 106 = 16 x109 byes/sec Cache Block Size L2 cache requires 3 CPU cycles to deliver 32 bytes, thus: Maximum L2 accesses per second = 500/3 x 106 = 166.67 x 106 accesses/second

Maximum effective L2 bandwidth = 32 x 166.67x 106 = 5,333.33x 106 = 5.33 x109 byes/sec L3 cache requires 6 CPU cycles to deliver 32 bytes, thus: Maximum L3 accesses per second = 500/6 x 106 = 83.33 x 106 accesses/second Maximum effective L3 bandwidth = 32 x 166.67x 106 = 2,666.67x 106 = 2.67 x109 byes/sec Memory requires 101 CPU cycles ( 101= M+1 = 100+1) to deliver 32 bytes, thus: Maximum main memory accesses per second = 500/101 x 106 = 4.95 x 106 accesses/second Maximum effective main memory bandwidth = 32 x 4.95x 106 = 158.42x 106 byes/sec Cache block size = 32 bytes CMPE550 - Shaaban #27 lec # 10 Spring 2017 4-24-2017 Program Steady-State Bandwidth-Usage Example For CPU with L1 Cache: B. What is the total number of memory accesses generated by the CPU per second? The total number of memory accesses generated by the CPU per second = (memory access/instruction) x clock rate / CPI = 1.3 x 500 x 106 / CPI = 650 x 106 / CPI With single L1 cache CPI was found = 7.6 CPU memory accesses = 650 x 106 / 7.6 = 85 x 106 accesses/sec C. What percentage of these memory accesses reach each cache level/memory and what percentage of each cache level/memory bandwidth is used by the CPU? For L1: The percentage of CPU memory accesses that reach L1 = 100% L1 Cache bandwidth usage = 32 x 85 x 106 = 2,720 x 106 = 2.7 x109 byes/sec Percentage of L1 bandwidth used = 2,720 / 16,000 = 0.17 or 17% (or by just dividing CPU accesses / peak L1 accesses = 85/500 = 0.17 = 17%) For Main Memory: The percentage of CPU memory accesses that reach main memory = (1-H1) = 0.05 or 5% Main memory bandwidth usage = 0.05 x 32 x 85 x 106 = 136 x 106 byes/sec Percentage of main memory bandwidth used = 136 / 158.42 = 0.8585 or 85.85% CMPE550 - Shaaban #28 lec # 10 Spring 2017 4-24-2017 Program Steady-State Bandwidth-Usage Example

B. For CPU with L1, L2 Cache: What is the total number of memory accesses generated by the CPU per second? The total number of memory accesses generated by the CPU per second = access/instruction) x clock rate / CPI = 1.3 x 500 x 106 / CPI = 650 x 106 / CPI With L1, L2 cache CPI was found = 3.778 CPU memory accesses = 650 x 106 / 3.778 = 172 x 106 accesses/sec (memory Vs. With L1 only = 85 x 106 accesses/sec C. What percentage of these memory accesses reach each cache level/memory and what percentage of each cache level/memory bandwidth is used by the CPU? For L1: The percentage of CPU memory accesses that reach L1 = 100% L1 Cache bandwidth usage = 32 x 172 x 106 = 5,505 x 106 = 5.505 x109 byes/sec Percentage of L1 bandwidth used = 5,505 / 16,000 = 0.344 or 34.4% Vs. With L1 only = 17% (or For L2: The percentage of CPU memory accesses that reach L2 = (I-H1) = 0.05 or 5% L2 Cache bandwidth usage = 0.05x 32 x 172 x 106 = 275.28 x 106 byes/sec Percentage of L2 bandwidth used = 275.28 / 5,333.33 = 0.0516 or 5.16% (or by just dividing CPU accesses / peak L1 accesses = 172/500 = 0.344 = 34.4%) by just dividing CPU accesses that reach L2 / peak L2 accesses = 0.05 x 172/ /166.67 = 8.6/ 166.67= 0.0516= 5.16%) For Main Memory: The percentage of CPU memory accesses that reach main memory = (1-H1) x (1-H2) = 0.05 x 0.4 = 0.02 or 2% Main memory bandwidth usage = 0.02 x 32 x 172 x 10 6 = 110.11 x 106 byes/sec Percentage of main memory bandwidth used = 110.11 / 158.42 = 0.695 or 69.5% Exercises: What if Level 1 (L1) is split?

What if Level 2 (L2) is write back with write allocate? Vs. With L1 only = 85.5% CMPE550 - Shaaban #29 lec # 10 Spring 2017 4-24-2017 Program Steady-State Bandwidth-Usage Example B. For CPU with L1, L2, L3 Cache: What is the total number of memory accesses generated by the CPU per second? The total number of memory accesses generated by the CPU per second = access/instruction) x clock rate / CPI = 1.3 x 500 x 10 6 / CPI = 650 x 106 / CPI With L1, L2, L3 cache CPI was found = 2.54 CPU memory accesses = 650 x 106 / 2.54 = 255.9 x 106 accesses/sec (memory Vs. With L1 only = 85 x 106 accesses/sec With L1, L2 = 172 x 106 accesses/sec C. What percentage of these memory accesses reach each cache level/memory and what percentage of each cache level/memory bandwidth is used by the CPU? For L1: The percentage of CPU memory accesses that reach L1 = 100% L1 Cache bandwidth usage = 32 x 255.9 x 10 6 = 8,188 x 106 = 8.188 x109 byes/sec Percentage of L1 bandwidth used = 8,188 / 16,000 = 0.5118 or 51.18% (or by just dividing CPU accesses / peak L1 accesses = 172/500 = 0.344 = 34.4%) Vs. With L1 only = 17% With L1, L2 = 34.4% For L2: The percentage of CPU memory accesses that reach L2 = (1-H1) = 0.05 or 5% L2 Cache bandwidth usage = 0.05x 32 x 255.9 x 10 6 = 409.45 x 106 byes/sec Percentage of L2 bandwidth used = 409.45 / 5,333.33 = 0.077 or 7.7 % (or by just dividing CPU accesses that reach L2 / peak L2 accesses = 0.05 x 255.9/ /166.67 = 12.795/ 166.67= 0.077= 7.7%)

For L3: The percentage of CPU memory accesses that reach L2 = (1-H1)x (1-H2) = 0.02 or 2% L3 Cache bandwidth usage = 0.02x 32 x 255.9 x 10 6 = 163.78 x 106 byes/sec Percentage of L3 bandwidth used = 163.78 / 2,666.67 = 0.061 or 6.1 % Vs. With L1, L2 only = 5.16% (or by just dividing CPU accesses that reach L3 / peak L3 accesses = 0.02 x 255.9/ /83.33 = 5.118/ 83.33= 0.061= 6.1%) For Main Memory: The percentage of CPU memory accesses that reach main memory = (1-H1) x (1-H2) x (1-H3)= .05 x .4 x.5 = 0.01 or 1% Main memory bandwidth usage = 0.01 x 32 x 255.9 x 10 6 = 81.89 x 106 byes/sec Percentage of main memory bandwidth used = 110.11 / 158.42 = 0.517 or 51.7% Vs. With L1 only = 85.5% With L1, L2 = 69.5% Exercises: What if Level 1 (L1) is split? What if Level 3 (L3) is write back with write allocate? CMPE550 - Shaaban #30 lec # 10 Spring 2017 4-24-2017 X86 CPU Dual Channel PC3200 DDR SDRAM Sample (Realistic?) Bandwidth Data Dual (64-bit) Channel PC3200 DDR SDRAM has a theoretical peak bandwidth of 400 MHz x 8 bytes x 2 = 6400 MB/s Is memory bandwidth still an issue? Source: The Tech Report 1-21-2004 http://www.tech-report.com/reviews/2004q1/athlon64-3000/index.x?pg=3 CMPE550 - Shaaban #31 lec # 10 Spring 2017 4-24-2017 X86 CPU Dual Channel PC3200 DDR SDRAM Sample (Realistic?) Latency Data 2.2GHz PC3200 DDR SDRAM has a theoretical latency range of 18-40 ns (not accounting for memory controller latency or other address/data line delays). (104 CPU Cycles) On-Chip

Memory Controller Lowers Effective Memory Latency (256 CPU Cycles) Source: The Tech Report (1-21-2004) http://www.tech-report.com/reviews/2004q1/athlon64-3000/index.x?pg=3 Is memory latency still an issue? CMPE550 - Shaaban #32 lec # 10 Spring 2017 4-24-2017 X86 CPU Cache/Memory Performance Example: AMD Athlon XP/64/FX Vs. Intel P4/Extreme Edition Intel P4 3.2 GHz Extreme Edition Data L1: 8KB Data L2: 512 KB Data L3: 2048 KB Intel P4 3.2 GHz Data L1: 8KB Data L2: 512 KB AMD Athon 64 FX51 2.2 GHz Data L1: 64KB Data L2: 1024 KB (exlusive) AMD Athon 64 3400+ 2.2 GHz Data L1: 64KB Data L2: 1024 KB (exclusive) AMD Athon 64 3200+ 2.0 GHz Data L1: 64KB Data L2: 1024 KB (exclusive) AMD Athon 64 3000+ 2.0 GHz Data L1: 64KB Data L2: 512 KB (exclusive) Main Memory: Dual (64-bit) Channel PC3200 DDR SDRAM peak bandwidth of 6400 MB/s Source: The Tech Report 1-21-2004 http://www.tech-report.com/reviews/2004q1/athlon64-3000/index.x?pg=3 AMD Athon XP 2.2 GHz Data L1: 64KB Data L2: 512 KB (exclusive) CMPE550 - Shaaban #33 lec # 10 Spring 2017 4-24-2017

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